1. Field of the Invention
The present invention relates to a semiconductor memory device which controls refresh of a memory array in normal operation, and particularly relates to a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) in which when receiving a refresh request at a predetermined refresh interval, one or more word lines selected based on a count value of a refresh counter can be refreshed.
2. Description of the Related Art
Generally, each memory cell of a DRAM should be refreshed at a predetermined refresh period in order to retain data stored as electric charge in the memory cell. In normal operation of an arbitrary bank of the DRAM, a refresh counter counts up a row address at every refresh interval defined in the specification and refresh is sequentially performed for the row address indicated by the count value. For example, on the assumption that 2m word lines corresponding to an m-bit row address are refreshed one by one at every refresh interval, the refresh period of each memory cell is 2m·t (t:refresh interval). However, storage capacity of the DRAM is increased recently, so the refresh period 2m·t is likely to be insufficient for data retention characteristics of the memory cell. Therefore, it is desirable to increase the frequency of refresh so that a refresh period adapted to an actual value of the data retention time of the memory cell is obtained.
To solve such a problem, a configuration in which two or more word lines are refreshed simultaneously at every refresh interval is employed (for example, see JP 2003-187578). For example, by configuring the refresh counter so as to be corresponded to the row address as shown in FIG. 13, two word lines can be refreshed simultaneously. In the example of FIG. 13, the refresh counter including 1-bit counters CNT0 to CNT12 connected in 13 stages is configured. A refresh request signal R is input to the refresh counter, and every time the refresh counter counts up.
The count value of the refresh counter is assigned to lower 13 bits A0 to A12 of the row address. Meanwhile, the most significant bit A13 of the row address is redundant and disconnected from the refresh counter. Thus, the lower 13 bits A0 to A12 are designated by the count value of the refresh counter, and two row addresses corresponding to the most significant bit A13 are selected to be refreshed regardless of whether the bit A13 is 0 or 1. Accordingly, refresh may be performed 213 times to complete refresh for all 214 word lines which can be designated by the row address, so that the refresh period is reduced to half.
In the above-mentioned conventional configuration of the DRAM, by increasing the number of word lines to be refreshed at every refresh interval from one to two, the refresh period can be reduced to half. However, when reducing the refresh period to half, it is assumed that the refresh period is likely to be too short for the actual value of the data retention time of the memory cell while slightly reduction thereof is sufficient in reality. That is, in the configuration in which one word line is refreshed at every refresh interval, it is insufficient in terms of the data retention characteristics of the memory cell, however in the configuration in which two word lines are refreshed, the frequency of the refresh is likely to be large so that extra current is consumed. If the memory cell has an actual data retention time which corresponds to refresh for about 1.5 word lines at every refresh interval, it is difficult to correspondingly adjust the refresh period, and therefore it is a problem that large current is consumed in refresh operation of the DRAM.